Module riscv64
RISC-V RV64 specific intrinsics
Modules
Functions
- _aes64ds
- _aes64dsm
- _aes64es
- _aes64esm
- _aes64im
- _sha512sig0
- _sha512sig1
- _sha512sum0
- _sha512sum1
- aes64ds AES final round decryption instruction for RV64.
- aes64dsm AES middle round decryption instruction for RV64.
- aes64es AES final round encryption instruction for RV64.
- aes64esm AES middle round encryption instruction for RV64.
- aes64im This instruction accelerates the inverse MixColumns step of the AES Block Cipher, and is used to aid creation of the decryption KeySchedule.
- aes64ks1i This instruction implements part of the KeySchedule operation for the AES Block cipher involving the SBox operation.
- aes64ks2 This instruction implements part of the KeySchedule operation for the AES Block cipher.
- hlv_d Loads virtual machine memory by double integer
- hlv_wu Loads virtual machine memory by unsigned word integer
- hsv_d Stores virtual machine memory by double integer
- sha512sig0 Implements the Sigma0 transformation function as used in the SHA2-512 hash function [49] (Section 4.1.3).
- sha512sig1 Implements the Sigma1 transformation function as used in the SHA2-512 hash function [49] (Section 4.1.3).
- sha512sum0 Implements the Sum0 transformation function as used in the SHA2-512 hash function [49] (Section 4.1.3).
- sha512sum1 Implements the Sum1 transformation function as used in the SHA2-512 hash function [49] (Section 4.1.3).