Module riscv32
RISC-V RV32 specific intrinsics
Modules
Functions
- _aes32dsi
- _aes32dsmi
- _aes32esi
- _aes32esmi
- _sha512sig0h
- _sha512sig0l
- _sha512sig1h
- _sha512sig1l
- _sha512sum0r
- _sha512sum1r
- _unzip
- _zip
- aes32dsi AES final round decryption instruction for RV32.
- aes32dsmi AES middle round decryption instruction for RV32.
- aes32esi AES final round encryption instruction for RV32.
- aes32esmi AES middle round encryption instruction for RV32 with.
- sha512sig0h Implements the high half of the Sigma0 transformation, as used in the SHA2-512 hash function [49] (Section 4.1.3).
- sha512sig0l Implements the low half of the Sigma0 transformation, as used in the SHA2-512 hash function [49] (Section 4.1.3).
- sha512sig1h Implements the high half of the Sigma1 transformation, as used in the SHA2-512 hash function [49] (Section 4.1.3).
- sha512sig1l Implements the low half of the Sigma1 transformation, as used in the SHA2-512 hash function [49] (Section 4.1.3).
- sha512sum0r Implements the Sum0 transformation, as used in the SHA2-512 hash function [49] (Section 4.1.3).
- sha512sum1r Implements the Sum1 transformation, as used in the SHA2-512 hash function [49] (Section 4.1.3).
- unzip Place odd and even bits of the source word into upper/lower halves of the destination.
- zip Place upper/lower halves of the source register into odd/even bits of the destination respectivley.